In many known processing systems there are several processors, or other circuits which include a processing unit (hereinafter referred to as masters), which are coupled to a common bus so that they can all access various slave devices also coupled to the bus, such as various types of memory devices, e.g. DRAMs, Static Random Access Memories (SRAMs), Read Only Memories (ROMs), or other types of peripheral devices, e.g. storage devices or communications interfaces. In some instances, however, a particular DRAM is only ever accessed by a single master device, so that it can be considered proprietary or private to that one master device.
The DRAMs are provided with Row Access Strobe (RAS) and Column Access Strobe (CAS) line inputs which are used for addressing a particular memory cell by its row and column address for both reading the cell and writing to the cell. A feature of the use of the RAS and CAS lines for addressing is that the RAS input is used to designate a so-called page of the DRAM, while the CAS input designates a particular location or address within that page, so that, as long as successive cells to be addressed are within the same page (so-called fast page mode), only the CAS input need be changed and the RAS input can remain asserted but does not need to be read each time, thus shortening the access cycle. This can only happen, of course, as long as the same master device has control of the bus, so that it can be sure that no other master device has accessed another page of the DRAM in between two of its accesses. Thus, every time the master device gains bus control, it must address using both RAS and CAS lines (so-called out-of-page access), which involves more time.
Furthermore, as is well known, DRAMs need to be refreshed in order for them to maintain the data in their memory cells, and this can be done by enabling first the CAS input and then the RAS input, instead of the RAS input first followed by the CAS input, as is done for addressing. Such refreshing needs to be done regularly so that the master device which controls the refreshing must obtain bus control, perform the refreshing and then relinquish control of the bus. This uses up valuable bus time, which could have been used by other master devices.
The present invention therefore seeks to provide a microprocessor for use with a private DRAM which overcomes, or at least reduces the above-mentioned problems of the prior art. The term "microprocessor" hereafter is intended to include all master devices.